2026
|
Chang, Chunlu; Tan, Fan; Zhao, Xingyu; Qi, Liujian; An, Junru; Liu, Zhilin; Shi, Yaru; Liu, Mingxiu; Che, Mengqi; Li, Yahui; Feng, Yanze; Zou, Yuting; Li, Dabing; Lanza, Mario; Zhang, Nan; Li, Shaojuan Boosting Artificial Olfaction: Visual Cues-Enhanced Gas Classification
by a Bimodal Neuromorphic Device ADVANCED MATERIALS, 38 (49), 2026, DOI: 10.1002/adma.74191. Abstract | BibTeX | Endnote @article{WOS:001826906800001,
title = {Boosting Artificial Olfaction: Visual Cues-Enhanced Gas Classification
by a Bimodal Neuromorphic Device},
author = {Chunlu Chang and Fan Tan and Xingyu Zhao and Liujian Qi and Junru An and Zhilin Liu and Yaru Shi and Mingxiu Liu and Mengqi Che and Yahui Li and Yanze Feng and Yuting Zou and Dabing Li and Mario Lanza and Nan Zhang and Shaojuan Li},
doi = {10.1002/adma.74191},
times_cited = {0},
issn = {0935-9648},
year = {2026},
date = {2026-09-01},
journal = {ADVANCED MATERIALS},
volume = {38},
number = {49},
publisher = {WILEY-V C H VERLAG GMBH},
address = {POSTFACH 101161, 69451 WEINHEIM, GERMANY},
abstract = {Artificial olfactory sensors have garnered significant attention in
various applications, including micro-robotics, implantable medical
devices, and consumer electronics. However, they still face challenges
in trade-offs among high recognition accuracy, compact size, and low
power consumption. Existing strategies can rely on large-scale sensor
arrays (up to 104 elements) to enhance gas recognition accuracy, but
this substantially increases system size and power consumption. Inspired
by biological multisensory synergy, we propose a visual-olfactory
bimodal neuromorphic device to overcome these limitations. It emulates
biological perceptual fusion, including bimodal perceptual weighting and
enhancement. With a small active area of 148 & micro;m2, a static power
consumption of only 3.4 & micro;W, and a low operating voltage of 1 V,
the device exhibits ppb-level sensing performance and is capable of both
classifying gas types and identifying concentrations for multiple target
gases. The proposed bimodal perception strategy achieves a gas
classification accuracy of 98.27%, far exceeding that of the olfactory
unimodal mode (52.24%), and, importantly, enables precise
discrimination of mixed gases with highly overlapping sensing
signatures. Our strategy not only provides a unit architecture for
constructing miniaturized, low-power, and highly accurate artificial
olfactory systems but also paves the way for next-generation
bio-inspired multimodal neuromorphic sensing.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Artificial olfactory sensors have garnered significant attention in
various applications, including micro-robotics, implantable medical
devices, and consumer electronics. However, they still face challenges
in trade-offs among high recognition accuracy, compact size, and low
power consumption. Existing strategies can rely on large-scale sensor
arrays (up to 104 elements) to enhance gas recognition accuracy, but
this substantially increases system size and power consumption. Inspired
by biological multisensory synergy, we propose a visual-olfactory
bimodal neuromorphic device to overcome these limitations. It emulates
biological perceptual fusion, including bimodal perceptual weighting and
enhancement. With a small active area of 148 & micro;m2, a static power
consumption of only 3.4 & micro;W, and a low operating voltage of 1 V,
the device exhibits ppb-level sensing performance and is capable of both
classifying gas types and identifying concentrations for multiple target
gases. The proposed bimodal perception strategy achieves a gas
classification accuracy of 98.27%, far exceeding that of the olfactory
unimodal mode (52.24%), and, importantly, enables precise
discrimination of mixed gases with highly overlapping sensing
signatures. Our strategy not only provides a unit architecture for
constructing miniaturized, low-power, and highly accurate artificial
olfactory systems but also paves the way for next-generation
bio-inspired multimodal neuromorphic sensing. - FNClarivate Analytics Web of Science
- VR1.0
- PTJ
- AFChunlu Chang
Fan Tan
Xingyu Zhao
Liujian Qi
Junru An
Zhilin Liu
Yaru Shi
Mingxiu Liu
Mengqi Che
Yahui Li
Yanze Feng
Yuting Zou
Dabing Li
Mario Lanza
Nan Zhang
Shaojuan Li
- TIBoosting Artificial Olfaction: Visual Cues-Enhanced Gas Classification
by a Bimodal Neuromorphic Device - SOADVANCED MATERIALS
- DTArticle
- ABArtificial olfactory sensors have garnered significant attention in
various applications, including micro-robotics, implantable medical
devices, and consumer electronics. However, they still face challenges
in trade-offs among high recognition accuracy, compact size, and low
power consumption. Existing strategies can rely on large-scale sensor
arrays (up to 104 elements) to enhance gas recognition accuracy, but
this substantially increases system size and power consumption. Inspired
by biological multisensory synergy, we propose a visual-olfactory
bimodal neuromorphic device to overcome these limitations. It emulates
biological perceptual fusion, including bimodal perceptual weighting and
enhancement. With a small active area of 148 & micro;m2, a static power
consumption of only 3.4 & micro;W, and a low operating voltage of 1 V,
the device exhibits ppb-level sensing performance and is capable of both
classifying gas types and identifying concentrations for multiple target
gases. The proposed bimodal perception strategy achieves a gas
classification accuracy of 98.27%, far exceeding that of the olfactory
unimodal mode (52.24%), and, importantly, enables precise
discrimination of mixed gases with highly overlapping sensing
signatures. Our strategy not only provides a unit architecture for
constructing miniaturized, low-power, and highly accurate artificial
olfactory systems but also paves the way for next-generation
bio-inspired multimodal neuromorphic sensing. - Z90
- PUWILEY-V C H VERLAG GMBH
- PAPOSTFACH 101161, 69451 WEINHEIM, GERMANY
- SN0935-9648
- VL38
- DI10.1002/adma.74191
- UTWOS:001826906800001
- ER
- EF
|
Yang, Jihoon; Yoon, Sohui; Im, Jaehong; Kim, Jaemin; Park, Seonghyeok; Park, Jaeeun; Kim, Seong-Jin; Lee, Zonghoon; Suh, Joonki; Jeong, Hongsik; Lanza, Mario; Lim, Dong-Hyeok; Kwon, Soon-Yong Deterministic Switching-Path Engineering of CMOS-Integrated 2D
Memristors for Neuromorphic Computing SMALL, 2026, DOI: 10.1002/smll.75285. Abstract | BibTeX | Endnote @article{WOS:001868386200001,
title = {Deterministic Switching-Path Engineering of CMOS-Integrated 2D
Memristors for Neuromorphic Computing},
author = {Jihoon Yang and Sohui Yoon and Jaehong Im and Jaemin Kim and Seonghyeok Park and Jaeeun Park and Seong-Jin Kim and Zonghoon Lee and Joonki Suh and Hongsik Jeong and Mario Lanza and Dong-Hyeok Lim and Soon-Yong Kwon},
doi = {10.1002/smll.75285},
times_cited = {0},
issn = {1613-6810},
year = {2026},
date = {2026-09-01},
journal = {SMALL},
publisher = {WILEY-V C H VERLAG GMBH},
address = {POSTFACH 101161, 69451 WEINHEIM, GERMANY},
abstract = {Two-dimensional (2D) memristors are promising for low-power and
high-speed neuromorphic hardware. However, their performance under
circuit-level constraints remains limited because resistive switching
relies on native defects, hindering precise control of filament
formation. Here, we report 2D MoTe2 memristors that integrate
deterministic switching-path density engineering with CMOS-compatible
one-transistor-one-memristor (1T-1 M) architectures. The devices exhibit highly linear and symmetric synaptic plasticity (alpha p/alpha d =
0.019/0.2), enabled by a balanced interplay between filament formation
and confinement. Furthermore, monolithic integration with silicon
transistors enables gate-tunable compliance control, which suppresses
variability and stabilizes array-level operation. The resulting 1T-1 M
arrays exhibit a wide dynamic range (similar to 22 & times;), and
minimal potentiation/depression variation (7.95%/6.22%). Device-aware
simulations based on multilayer perception, convolutional neural
network, and autoencoder models confirm improved learning accuracy
compared to passive arrays. This work establishes a materials-to-circuit
design framework that links defect-path engineering with
transistor-assisted current control, providing a practical pathway
toward 2D neuromorphic hardware.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Two-dimensional (2D) memristors are promising for low-power and
high-speed neuromorphic hardware. However, their performance under
circuit-level constraints remains limited because resistive switching
relies on native defects, hindering precise control of filament
formation. Here, we report 2D MoTe2 memristors that integrate
deterministic switching-path density engineering with CMOS-compatible
one-transistor-one-memristor (1T-1 M) architectures. The devices exhibit highly linear and symmetric synaptic plasticity (alpha p/alpha d =
0.019/0.2), enabled by a balanced interplay between filament formation
and confinement. Furthermore, monolithic integration with silicon
transistors enables gate-tunable compliance control, which suppresses
variability and stabilizes array-level operation. The resulting 1T-1 M
arrays exhibit a wide dynamic range (similar to 22 & times;), and
minimal potentiation/depression variation (7.95%/6.22%). Device-aware
simulations based on multilayer perception, convolutional neural
network, and autoencoder models confirm improved learning accuracy
compared to passive arrays. This work establishes a materials-to-circuit
design framework that links defect-path engineering with
transistor-assisted current control, providing a practical pathway
toward 2D neuromorphic hardware. - FNClarivate Analytics Web of Science
- VR1.0
- PTJ
- AFJihoon Yang
Sohui Yoon
Jaehong Im
Jaemin Kim
Seonghyeok Park
Jaeeun Park
Seong-Jin Kim
Zonghoon Lee
Joonki Suh
Hongsik Jeong
Mario Lanza
Dong-Hyeok Lim
Soon-Yong Kwon
- TIDeterministic Switching-Path Engineering of CMOS-Integrated 2D
Memristors for Neuromorphic Computing - SOSMALL
- DTArticle
- ABTwo-dimensional (2D) memristors are promising for low-power and
high-speed neuromorphic hardware. However, their performance under
circuit-level constraints remains limited because resistive switching
relies on native defects, hindering precise control of filament
formation. Here, we report 2D MoTe2 memristors that integrate
deterministic switching-path density engineering with CMOS-compatible
one-transistor-one-memristor (1T-1 M) architectures. The devices exhibit highly linear and symmetric synaptic plasticity (alpha p/alpha d =
0.019/0.2), enabled by a balanced interplay between filament formation
and confinement. Furthermore, monolithic integration with silicon
transistors enables gate-tunable compliance control, which suppresses
variability and stabilizes array-level operation. The resulting 1T-1 M
arrays exhibit a wide dynamic range (similar to 22 & times;), and
minimal potentiation/depression variation (7.95%/6.22%). Device-aware
simulations based on multilayer perception, convolutional neural
network, and autoencoder models confirm improved learning accuracy
compared to passive arrays. This work establishes a materials-to-circuit
design framework that links defect-path engineering with
transistor-assisted current control, providing a practical pathway
toward 2D neuromorphic hardware. - Z90
- PUWILEY-V C H VERLAG GMBH
- PAPOSTFACH 101161, 69451 WEINHEIM, GERMANY
- SN1613-6810
- DI10.1002/smll.75285
- UTWOS:001868386200001
- ER
- EF
|
Liu, Lixin; Wei, Yimin; Liu, Kailang; Liu, Zhibo; Qin, Lanhao; Yuan, Yue; Xu, Yongshan; Huang, Bingrong; Liu, Jie; Ma, Yiran; Wei, Xiaofu; Fu, Yingshuang; Li, Huiqiao; Lanza, Mario; Zhai, Tianyou Highly Tunable Schottky Barrier to 2D Semiconductors Enabled by an
Inorganic-Molecular-Crystal Tunneling Layer ADVANCED MATERIALS, 2026, DOI: 10.1002/adma.74761. Abstract | BibTeX | Endnote @article{WOS:001855125100001,
title = {Highly Tunable Schottky Barrier to 2D Semiconductors Enabled by an
Inorganic-Molecular-Crystal Tunneling Layer},
author = {Lixin Liu and Yimin Wei and Kailang Liu and Zhibo Liu and Lanhao Qin and Yue Yuan and Yongshan Xu and Bingrong Huang and Jie Liu and Yiran Ma and Xiaofu Wei and Yingshuang Fu and Huiqiao Li and Mario Lanza and Tianyou Zhai},
doi = {10.1002/adma.74761},
times_cited = {0},
issn = {0935-9648},
year = {2026},
date = {2026-08-01},
journal = {ADVANCED MATERIALS},
publisher = {WILEY-V C H VERLAG GMBH},
address = {POSTFACH 101161, 69451 WEINHEIM, GERMANY},
abstract = {Effective tuning of the Schottky barrier, which determines charge
transport across the metal-semiconductor interface, is essential for
optimizing the performance of electronics and optoelectronic devices.
However, interfacial disorders and orbital overlap between metals and
semiconductors induce Fermi-level pinning (FLP), making the Schottky
barrier height (SBH) largely insensitive to metal work function. Here,
we demonstrate that depositing an ultrathin inorganic molecular crystal
layer of Sb2O3 between metal and 2D semiconductors can eliminate FLP,
enabling highly tunable SBH modulation. Owing to its van der Waals
structure, Sb2O3 introduces no excess defects and protects the fragile
2D channel from metal deposition damage, yielding a clean, defect-free
interface. Incorporation of Sb2O3 tunneling layer significantly reduces
the SBH in 2D MoS2 transistors, and the polarity of 2D WSe2-based FET
can be switched from n-type to p-type via adjusting the contact metal
work function. The pinning factor turns from -0.11 to around -0.93,
approaching the ideal Mott-Schottky limit. This scalable strategy offers
broad applicability in high-performance 2D electronics.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Effective tuning of the Schottky barrier, which determines charge
transport across the metal-semiconductor interface, is essential for
optimizing the performance of electronics and optoelectronic devices.
However, interfacial disorders and orbital overlap between metals and
semiconductors induce Fermi-level pinning (FLP), making the Schottky
barrier height (SBH) largely insensitive to metal work function. Here,
we demonstrate that depositing an ultrathin inorganic molecular crystal
layer of Sb2O3 between metal and 2D semiconductors can eliminate FLP,
enabling highly tunable SBH modulation. Owing to its van der Waals
structure, Sb2O3 introduces no excess defects and protects the fragile
2D channel from metal deposition damage, yielding a clean, defect-free
interface. Incorporation of Sb2O3 tunneling layer significantly reduces
the SBH in 2D MoS2 transistors, and the polarity of 2D WSe2-based FET
can be switched from n-type to p-type via adjusting the contact metal
work function. The pinning factor turns from -0.11 to around -0.93,
approaching the ideal Mott-Schottky limit. This scalable strategy offers
broad applicability in high-performance 2D electronics. - FNClarivate Analytics Web of Science
- VR1.0
- PTJ
- AFLixin Liu
Yimin Wei
Kailang Liu
Zhibo Liu
Lanhao Qin
Yue Yuan
Yongshan Xu
Bingrong Huang
Jie Liu
Yiran Ma
Xiaofu Wei
Yingshuang Fu
Huiqiao Li
Mario Lanza
Tianyou Zhai
- TIHighly Tunable Schottky Barrier to 2D Semiconductors Enabled by an
Inorganic-Molecular-Crystal Tunneling Layer - SOADVANCED MATERIALS
- DTArticle
- ABEffective tuning of the Schottky barrier, which determines charge
transport across the metal-semiconductor interface, is essential for
optimizing the performance of electronics and optoelectronic devices.
However, interfacial disorders and orbital overlap between metals and
semiconductors induce Fermi-level pinning (FLP), making the Schottky
barrier height (SBH) largely insensitive to metal work function. Here,
we demonstrate that depositing an ultrathin inorganic molecular crystal
layer of Sb2O3 between metal and 2D semiconductors can eliminate FLP,
enabling highly tunable SBH modulation. Owing to its van der Waals
structure, Sb2O3 introduces no excess defects and protects the fragile
2D channel from metal deposition damage, yielding a clean, defect-free
interface. Incorporation of Sb2O3 tunneling layer significantly reduces
the SBH in 2D MoS2 transistors, and the polarity of 2D WSe2-based FET
can be switched from n-type to p-type via adjusting the contact metal
work function. The pinning factor turns from -0.11 to around -0.93,
approaching the ideal Mott-Schottky limit. This scalable strategy offers
broad applicability in high-performance 2D electronics. - Z90
- PUWILEY-V C H VERLAG GMBH
- PAPOSTFACH 101161, 69451 WEINHEIM, GERMANY
- SN0935-9648
- DI10.1002/adma.74761
- UTWOS:001855125100001
- ER
- EF
|
Wu, Ernest Y; Grasser, Tibor; Lanza, Mario Industrial reliability testing of transistor gate dielectrics NATURE ELECTRONICS, 9 (7), pp. 726-732, 2026, DOI: 10.1038/s41928-026-01644-x. Abstract | BibTeX | Endnote @article{WOS:001801068400001,
title = {Industrial reliability testing of transistor gate dielectrics},
author = {Ernest Y Wu and Tibor Grasser and Mario Lanza},
doi = {10.1038/s41928-026-01644-x},
times_cited = {2},
issn = {2520-1131},
year = {2026},
date = {2026-07-01},
journal = {NATURE ELECTRONICS},
volume = {9},
number = {7},
pages = {726-732},
publisher = {NATURE PORTFOLIO},
address = {HEIDELBERGER PLATZ 3, BERLIN, 14197, GERMANY},
abstract = {Transistors are currently undergoing a reinvention due to the stagnation
of lateral scaling, the advance of three-dimensional stacking and the
introduction of novel nanomaterials such as two-dimensional materials. A
critical issue in the development of novel transistors is gate
dielectric reliability, as the dielectric needs to withstand high
electrical fields and block charge transport to guarantee correct device
functioning. However, while attempts have been made in the academic
literature to benchmark the figures of merit of transistors, the
methodologies proposed for the study of gate dielectrics typically do
not match industrial requirements. Here we explore how to evaluate the
reliability of a dielectric material in an industry-relevant manner. We
examine how industry benchmarks the performance of gate dielectrics in
silicon transistors, how to collect and analyse gate dielectric
reliability data to extract meaningful and industry-relevant
conclusions, and how to apply this to two-dimensional transistors using
gate dielectrics such as CaF2 and hexagonal boron nitride. We provide,
in particular, a data processing protocol to extract lifetime-specific
maximum allowed use voltage from ramped voltage stress, and provide an
Excel file as a simple tool to carry out this extraction.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Transistors are currently undergoing a reinvention due to the stagnation
of lateral scaling, the advance of three-dimensional stacking and the
introduction of novel nanomaterials such as two-dimensional materials. A
critical issue in the development of novel transistors is gate
dielectric reliability, as the dielectric needs to withstand high
electrical fields and block charge transport to guarantee correct device
functioning. However, while attempts have been made in the academic
literature to benchmark the figures of merit of transistors, the
methodologies proposed for the study of gate dielectrics typically do
not match industrial requirements. Here we explore how to evaluate the
reliability of a dielectric material in an industry-relevant manner. We
examine how industry benchmarks the performance of gate dielectrics in
silicon transistors, how to collect and analyse gate dielectric
reliability data to extract meaningful and industry-relevant
conclusions, and how to apply this to two-dimensional transistors using
gate dielectrics such as CaF2 and hexagonal boron nitride. We provide,
in particular, a data processing protocol to extract lifetime-specific
maximum allowed use voltage from ramped voltage stress, and provide an
Excel file as a simple tool to carry out this extraction. - FNClarivate Analytics Web of Science
- VR1.0
- PTJ
- AFErnest Y Wu
Tibor Grasser
Mario Lanza
- TIIndustrial reliability testing of transistor gate dielectrics
- SONATURE ELECTRONICS
- DTArticle
- ABTransistors are currently undergoing a reinvention due to the stagnation
of lateral scaling, the advance of three-dimensional stacking and the
introduction of novel nanomaterials such as two-dimensional materials. A
critical issue in the development of novel transistors is gate
dielectric reliability, as the dielectric needs to withstand high
electrical fields and block charge transport to guarantee correct device
functioning. However, while attempts have been made in the academic
literature to benchmark the figures of merit of transistors, the
methodologies proposed for the study of gate dielectrics typically do
not match industrial requirements. Here we explore how to evaluate the
reliability of a dielectric material in an industry-relevant manner. We
examine how industry benchmarks the performance of gate dielectrics in
silicon transistors, how to collect and analyse gate dielectric
reliability data to extract meaningful and industry-relevant
conclusions, and how to apply this to two-dimensional transistors using
gate dielectrics such as CaF2 and hexagonal boron nitride. We provide,
in particular, a data processing protocol to extract lifetime-specific
maximum allowed use voltage from ramped voltage stress, and provide an
Excel file as a simple tool to carry out this extraction. - Z92
- PUNATURE PORTFOLIO
- PAHEIDELBERGER PLATZ 3, BERLIN, 14197, GERMANY
- SN2520-1131
- VL9
- BP726
- EP732
- DI10.1038/s41928-026-01644-x
- UTWOS:001801068400001
- ER
- EF
|
Pazos, Sebastian; Fontana, Andres; Shen, Yaqing; Yuan, Yue; Yu, Yiyang; Shamim, Atif; Psychogiou, Dimitra; Lanza, Mario Reconfigurable mmWave microchips co-integrating hBN switches on GaN NATURE, 655 (8124), 2026, DOI: 10.1038/s41586-026-10761-8. Abstract | BibTeX | Endnote @article{WOS:001814240100001,
title = {Reconfigurable mmWave microchips co-integrating hBN switches on GaN},
author = {Sebastian Pazos and Andres Fontana and Yaqing Shen and Yue Yuan and Yiyang Yu and Atif Shamim and Dimitra Psychogiou and Mario Lanza},
doi = {10.1038/s41586-026-10761-8},
times_cited = {2},
issn = {0028-0836},
year = {2026},
date = {2026-07-01},
journal = {NATURE},
volume = {655},
number = {8124},
publisher = {NATURE PORTFOLIO},
address = {HEIDELBERGER PLATZ 3, BERLIN, 14197, GERMANY},
abstract = {Monolithic microwave integrated circuits (MMICs) are an emerging
technology that is expected to substantially improve telecommunications
in the next few years1,2. MMICs use application-specific semiconductors
to meet the performance needs of 5G standards and beyond; however,
integrating high-frequency switches into these platforms is very
demanding in terms of area and cost and doing so is also a bottleneck
for performance3. Memristive radio-frequency switches are an appealing
alternative due to their easy fabrication and high device-level
electrical performance, but their use in circuit implementations of
MMICs has never been realized4. Here we demonstrate programmable
millimetre-wave (mmWave) gallium nitride (GaN) MMICs fabricated with
memristive radio-frequency switches made from two-dimensional layered
hexagonal boron nitride (hBN) integrated directly on the
back-end-of-line. We fabricated back-end-of-line wideband switches
operating up to 100 GHz with insertion losses as low as 0.3 dB and
isolation better than 15 dB. The switches delivered long-term state
retention (2 weeks), stable on-state resistance at 175 degrees C, linear
power handling within 0.28 dB measured up to 18 dBm, and an extrapolated
1-dB compression point mean of 30.52 dBm. We use one-transistor,
one-memristor cell integration for the switch drivers, achieving 3,250
cycles of endurance, an improvement for two-dimensional-material-based
memristive radio-frequency switches. Finally, we demonstrate the
implementation of memristive-configurable attenuators, power dividers
and programmable resonators on the GaN MMIC platform.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Monolithic microwave integrated circuits (MMICs) are an emerging
technology that is expected to substantially improve telecommunications
in the next few years1,2. MMICs use application-specific semiconductors
to meet the performance needs of 5G standards and beyond; however,
integrating high-frequency switches into these platforms is very
demanding in terms of area and cost and doing so is also a bottleneck
for performance3. Memristive radio-frequency switches are an appealing
alternative due to their easy fabrication and high device-level
electrical performance, but their use in circuit implementations of
MMICs has never been realized4. Here we demonstrate programmable
millimetre-wave (mmWave) gallium nitride (GaN) MMICs fabricated with
memristive radio-frequency switches made from two-dimensional layered
hexagonal boron nitride (hBN) integrated directly on the
back-end-of-line. We fabricated back-end-of-line wideband switches
operating up to 100 GHz with insertion losses as low as 0.3 dB and
isolation better than 15 dB. The switches delivered long-term state
retention (2 weeks), stable on-state resistance at 175 degrees C, linear
power handling within 0.28 dB measured up to 18 dBm, and an extrapolated
1-dB compression point mean of 30.52 dBm. We use one-transistor,
one-memristor cell integration for the switch drivers, achieving 3,250
cycles of endurance, an improvement for two-dimensional-material-based
memristive radio-frequency switches. Finally, we demonstrate the
implementation of memristive-configurable attenuators, power dividers
and programmable resonators on the GaN MMIC platform. - FNClarivate Analytics Web of Science
- VR1.0
- PTJ
- AFSebastian Pazos
Andres Fontana
Yaqing Shen
Yue Yuan
Yiyang Yu
Atif Shamim
Dimitra Psychogiou
Mario Lanza
- TIReconfigurable mmWave microchips co-integrating hBN switches on GaN
- SONATURE
- DTArticle
- ABMonolithic microwave integrated circuits (MMICs) are an emerging
technology that is expected to substantially improve telecommunications
in the next few years1,2. MMICs use application-specific semiconductors
to meet the performance needs of 5G standards and beyond; however,
integrating high-frequency switches into these platforms is very
demanding in terms of area and cost and doing so is also a bottleneck
for performance3. Memristive radio-frequency switches are an appealing
alternative due to their easy fabrication and high device-level
electrical performance, but their use in circuit implementations of
MMICs has never been realized4. Here we demonstrate programmable
millimetre-wave (mmWave) gallium nitride (GaN) MMICs fabricated with
memristive radio-frequency switches made from two-dimensional layered
hexagonal boron nitride (hBN) integrated directly on the
back-end-of-line. We fabricated back-end-of-line wideband switches
operating up to 100 GHz with insertion losses as low as 0.3 dB and
isolation better than 15 dB. The switches delivered long-term state
retention (2 weeks), stable on-state resistance at 175 degrees C, linear
power handling within 0.28 dB measured up to 18 dBm, and an extrapolated
1-dB compression point mean of 30.52 dBm. We use one-transistor,
one-memristor cell integration for the switch drivers, achieving 3,250
cycles of endurance, an improvement for two-dimensional-material-based
memristive radio-frequency switches. Finally, we demonstrate the
implementation of memristive-configurable attenuators, power dividers
and programmable resonators on the GaN MMIC platform. - Z92
- PUNATURE PORTFOLIO
- PAHEIDELBERGER PLATZ 3, BERLIN, 14197, GERMANY
- SN0028-0836
- VL655
- DI10.1038/s41586-026-10761-8
- UTWOS:001814240100001
- ER
- EF
|